AEC-Q007-2024 Board Level Reliability (BLR) testing - for Automotive Electronics and High-Performance Computing AI Server Applications
To ensure these electronic components met the highest standards for operating resilience in high-temperature and high-heat running environments, The Automotive Electronics Council (AEC) released a set of standards, including the family members of the AEC Component Technical Committee - AEC-Q100 (for IC Chips), AEC-Q101 (for Discrete Components), AEC-Q102 (for Discrete Optoelectronic Components), AEC-Q103 (for MEMS, Microelectromechanical Systems), AEC-Q104 (for MCM, Multi-Chip Modules), and AEC-Q200 (for Passive Components).
AEC released the AEC-Q007 specification in March 2024, which is for automotive Board Level Reliability (BLR) testing, designed in conjunction with PCB that details the test methods for automotive PCB and daisy chain. It elaborates on PCB and Daisy Chain designs, with Daisy Chain design being the BLR board-level reliability test commonly heard in the industry.
Board-level reliability
https://insights.globalspec.com/article/23190/a-new-path-to-board-level-reliability
Ensuring board-level reliability (BLR) is particularly challenging in industries such as automotive and high-performance computing, which drive artificial intelligence (AI). In each, harsh operating environments and additional demands are increasing reliability requirements and PCB complexity. Add to this the fact that the interconnect between board and component can be a system’s weakest link, and the scope of the task becomes clear on AEC-Q007-2024 Board Level Reliability (BLR) testing.
AEC-Q007-2024 Board Level Reliability (BLR) testing - for Automotive Electronics and High-Performance Computing AI Server Applications
In the past, AEC only verified the parts. AEC-Q007-2024 takes PCB into consideration for the first time. The Board Level Reliability (BLR) testing method by AEC-Q007-2024 is to verify the parts with PCB and to design the solder balls on PCB into a conductive mode to create a loop to observe the lifespan of solder joints. The solder joints life have been observed, during the BLR testing process conducted by King Son TSC Thermal Stress Complex Test Chamber, the measurement instrument, King Son VMR-S Conductor Resistance Evaluation System – Standard is used to conduct and to obtain real-time dynamic measurements information at high speed and instantly determine the solder joint yield (on-resistance should be below <20%). The purpose of the AEC-Q007-2024 testing is not to distinguish whether the parts are pass or failure, the important thing is to understand and to collect the characteristics of the parts and design the layout on the PCB board, therefore, that can conduct the temperature cycle testing for failure distribution of PCB and solder balls as a reference for subsequent design improvements.The principle of BLR verification involves designing the solder joints and PCB in a conductive mode to create a loop to observe the lifespan of solder joints. During the testing process, measurement equipment is used to obtain real-time information for determining solder joint yield. In AEC-Q007, Daisy Chain design is divided into four levels, with Level 3 being the simplest and Level 0 being the most complex in terms of design difficulty.
The BLR testing process needs to be dynamically monitored. The testing methods, temperature Cycling Requirements, mandated and preferred test parameters within mandated Conditions refer to the IPC-9701 specification. The temperature cycle in high and low temperature dwell time is preferably recommended to be 10~15 minutes. The IPC-9701 specification also emphasizes that exposure of assemblies to cyclic temperature changes where the rate of temperature change is slow enough to avoid thermal shock (typically less than or equal to 20°C [36°F]/min).
AEC-Q007 provides design recommendations for automotive electronics use PCBs. The number of layer recommended for automotive electronics use PCB is 8 layers (copper) and a thickness of 1.6mm.
AEC-Q007-2024 Board Level Reliability (BLR) Testing Method
Via Testing and Failure
Solder Ball Failure
Mode 1: The crack occurs on the base plate and the entire ball pad is pulled up.Mode 2: Cracks occur in the intermetallic compound close to the substrate.
Mode 3: Cracks occur close to the substrate and break solder ball joints and intermetallic compounds.
Mode 4: The crack occurs close to the end of the testing board, and the break occurs between the solder ball joint and the intermetallic compound.
Mode 5: The crack occurs in the dimetallic compound close to the end of the testing board.
Mode 6: Cracks occur on the test plate, pulling up the entire ball pad.
AEC-Q007-2024 testing temperature range and temperature change rate
The BRL testing process that needs to be conducted dynamically monitored by King Son VMR-S Conductor Resistance Evaluation System – Standard. The testing methods, temperature Cycling Requirements, mandated and preferred test parameters within mandated Conditions refer to the IPC-9701 specification. The temperature cycle in high and low temperature dwell time is preferably recommended to be 10~15 minutes. The IPC-9701 specification also emphasizes that exposure of assemblies to cyclic temperature changes where the rate of temperature changeis slow enough to avoid thermal shock (typically less than or equal to 20°C [36°F]/min).
The testing temperature range selection is not based on the reliability testing temperature of the tested samples but on the actual temperature range used for the tested samples.
AEC-Q007-2024 Temperature Cycling Conditions Interpretation
- The temperature change for the temperature cycle is adopted by a single tank with the samples under tested that does not move, instead of a double tank with the samples under tested moving.
- The temperature must meet or exceed the expected operating temperature range of the application environment, aimed to test the life of automotive board-level reliability (BLR), not semiconductor devices.
- The temperature control is by the air temperature
- The dwell temperature tolerance of the samples to be tested
- First choice is by heating (5/-0℃), chilling (-5/+0℃)
- Second choice is by heating (+10/-0℃), chilling ( - 10/+0℃)
- The temperature change rate is not the heating rising rate of the samples to be tested but is the upper limit. A common temperature change rate is 10°C/min. Below 5°C/min that is proved impractical in experiments.
- The temperature change rate is measured from the temperature under or near the samples to be tested, it is usually 10℃/min and not less than 5℃/min.
- The dwell time 10~15 min. can generate to provide approximately equal damage and crack growth.
- Excessive dwell time will lead to shortened the lifespan of tested samples.
- The sample size for each experiment is 50 in one batch (as close as possible, IPC-9701 sample size is 32)
- Once the failure rate is higher than 63.2%, the experiment will be terminated.
- The measurement report must record the air temperature and the temperature of samples to be tested.
IPC-9701 application scope (reference with AEC-Q007-2024 specification)
1.SCOPE
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This specification establishes specific test methods to evaluate the performance and reliability of surface mount solder attachments of electronic assemblies. It further establishes different levels of performance and reliability of the solder attachments of surface mount devices to rigid, flexible and rigid-flex circuit structures. In addition, it provides an approximate means of relating the results from these performance tests to the reliability of solder attachments for the use environments and conditions of electronic assemblies.
1.1 Purpose
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The purpose of this document is:
- To provide confidence that the design and the manufacturing/assembly processes create a product that is capable of meeting its intended goals.
- To permit the analytical prediction of reliability based on a generic database and technical understanding.
- To provide standardized test methods and reporting procedures.
IPC-9701A: Temperature Cycling Requirements, Mandated and Preferred Test Parameters Within Mandated Conditions
| Testing Conditions | QUALIFICATION REQUIREMENTS | ||
| ED-4702A (Mechanical stress test methods for semiconductor surface mounting devices) | IPC 9701 (Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments | ||
| Testing temperature (Highest testing temperature） |
TCA: -30℃←→+80℃ | TC1: 0℃←→+100℃ (First choice) | |
| TCB: -25℃←→+125℃ | TC2: -25℃←→+100℃ | ||
| TCC: -40℃←→+125℃ | TC3: -40℃←→+125℃ | ||
| TCD: -65℃←→+125℃ | TC4: -55℃←→+125℃ | ||
| TCE: Lowest←→Highest (Normally 25℃←→70℃) | TC5: -55℃←→+100℃ | ||
| Number of Thermal Cycle (NTC) Requirement |
Equivalent to 5 years? | Equivalent to 10 years? | Test until the cumulative failure of the sample reaches 50% (preferably 63.2%) |
| TCA:1217cycles | TCA:2433cycles | 200cycles | |
| TCB:435cycles | TCB:869cycles | 500cycles | |
| TCC:365cycles | TCC:730cycles | 1000cycles(First choices are TC2、TC3、TC4) | |
| TCD:277cycles | TCD:553cycles | 3000cycles | |
| TCE:1825cycles | TCE:3650cycles | 6000cycles (First choice TC1) | |
| Low Temperature Dwell (Sample temperature) | 7 minutes | 10 minutes | |
| Low Temperature Temperature Tolerance (preferred) |
(+0℃/-10℃) | +0℃/-10℃、preferably (+0℃/-5℃) | |
| High Temperature Dwell (Sample temperature) | 7 minutes | 10 minutes | |
| Temperature Ramp Rate | 1.5 minutes (low temperature to high temperature) | <20℃/min [JESD22-A104 typical heating rate 15℃/min, preferably recommended temperature change 10~14℃/min] | |
| Full Production Sample Size | Not specific requirements | 33 component samples (32 test samples plus one for cross-section, add additional 10 samples for rework, if applicable) | |
| Printed Wiring (Circuit) Board (PWB/PCB) Thickness | 0.6～2.4mm | 2.35mm～3.15mm (>40mm for package size) | |
| Package/Die/ MCM（Multi-Chip Module） |
Daisy chain structure of die/package/ MCM（Multi-Chip Module） | Daisy chain structure of die/package/ MCM（Multi-Chip Module） | |
| Test Monitoring during testing | Daisy chain diagram for continuous measurement, the sampling frequency depends on the actual testing status | Use continuously dynamic measurement or data collection systems | |
| Failure definition | Not specific requirements | Scan all Daisy chains that must be completed within 1 minute, in which each dwell time must be scanned and recorded for 5-times readings, that when on-resistance >20% is considered as the failure and 10 failures are recorded. | |
IPC-9701 temperature cycle testing curve (refer to JESD22-A-104-B)
IPC9701 specification requirements:
1.The samples to be tested are put by parallel to the direction of wind, 2 samples places in the middle area and 4 samples around it.
2.Measure the temperature of six tested boards at different locations.
3.The slope is related to the loading of samples, the slope should be verified after adding the loading on testing samples.
IPC-9701 definition on dwell time and temperature
